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MOSEL VITELIC
MS622424 HIGH PERFORMANCE 8K x 24 BIT CMOS COLOR MAP
MS622424
Features
s Color Index Mode supports up to 8192 simultaneous colors out of 16.7 million total colors s 24-bit RGB Mode allows full true color display s High-speed operation capable of supporting resolutions up 1280 x 1024 s Available in 100-pin PQFP and MQUAD packages s Unique "Write-Buffer" at MPU port permits dualport-like operation using an economical singleport memory core s All TTL compatible inputs and outputs s 60, 70 and 80 MHz pipelined operation s Standard MPU Interface
Description
The MS622424 is a high performance, full CMOS, 8K x 24, 192K-bit pipelined static memory. This device is specifically designed for use as a color look-up table in high resolution video display systems. When two of these devices are operated in parallel, the resulting system will be capable of supporting a display of 1280 x 1024 bit mapped color graphics with 13 bits per pixel in the Color Index Mode or 24 bits per pixel in the RGB Mode. In the Color Index Mode, three internal 8Kx8's provide 8192 simultaneous colors from a 16.7 million color palette. The palette can be partitioned into several smaller palettes thereby supporting multiple window display. In the RGB Mode, the 24bit input can be gamma corrected on one of three gamma correction tables. The 24-bit gamma corrected value will then be presented at the output. This device is implemented in full CMOS for low power consumption, and is available in an 100-pin plastic or metal quad-flat-pack.
Functional Block Diagram
PIX.RGB(MUX CONTROL) PIXIN(0-12) PIXIN(0-7) PIXIN(0-12) PIXIN(8-15) PIXIN(0-12) PIXIN(16-23) ADDR 13 RGB 24 MPU CONTROL 13 13 13 13 13 13 8 8 8 OUTPUT LATCH
PIXIN(0-23) INPUT LATCH PIX.RGB(0-1) CEB1 CEB2 R/WB CONFIGSEL(0-2) CONFIGBUS(0-7) CBLANKB RSB BD.REV(0-3) CLOCK.IN PIPE.IN(0-3)
2:1 MUX 2:1 MUX 2:1 MUX
3:1 MUX 3:1 MUX 3:1 MUX
8Kx8 8Kx8 8Kx8
POUT(0-23)
64X37 WRITE FIFO
FIFO ADDR 13 FIFO RGB 24 24 AFB FFB
PIPELINE SYNCHRONIZATION PATH
PIPE.OUT(0-3)
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MOSEL VITELIC
Functional Description
MPU Interface The MPU interface allows the MPU to access the internal registers and the color map. The CONFIGSEL0-CONFIGSEL2 bits that are latched on the falling edge of CEB define the access mode. The access modes are defined in the table below. The R/WB pin is also latched on the falling edge of CEB and indicates a read operation when high and a write operation when low. These functions are illustrated in the truth table on the next page. The RGB0 and RGB1 bits are the two bits of a modulo 3 counter, which determine which color (red, green, or blue, in that order) is selected. These two bits are reset by a write to either the high or low Address Register. In writes and reads to and from the color palette, the Address Register is incremented at the end of the RGB cycle. In order to perform color pallette read without asynchronous problems, initialization is required. This is done by writing a command of configsel(2:0)=111 before the actual read starts. Upon finishing the color palette read operation, a read command of configsel(2:0)=111 should also be issued to switch MPU Access modes. During a read from the color palette, the color data output at POUT0-POUT23 may be disturbed because the address register will take over addressing of the color map. To prevent random color data from being displayed on the screen, the data at POUT0-POUT23 will be held at the value defined by the last valid pixel address for the duration of the read. A read of the color palette should not be performed while the Write FIFO is not empty because it may contend with the FIFO to color map write. It is recommended that FIFO empty flag status always be checked before issuing color palette read instructions. If such a contention occurs, then the color palette read will be disturbed by the write cycle. Write FIFO The Write FIFO stores data and addresses that are written to the Color Palette Buffer and Address Registers. The FIFO is emptied by writing the data to the color map during a blanking period as indicated by CBLANKB. The host can write up to 64 locations that contain a 13-bit address and a 24-bit MPU Access Modes
CONFIGSEL<2:0> 000 001 010 011 100 101 110 111 MODE
MS622424
Address Register low (R/W) Address Register high (R/W) Color Palette Buffer (R/W) Command Register (R/W) Status Register (read only) Color Buffer Register (read only) Revision register (read only) Color Palette read initialization (R/W)
color before the FIFO becomes full. When the FIFO is full the full flag pin (FFB) goes low until at least one location of the FIFO is transferred to the color map. If the host attempts to write to the Color Palette Buffer while the FFB is active, then the device will transfer 4 locations from the FIFO to the color map in order to make room for the incoming data, regardless of the state of CBLANKB. This process may disturb the data in the pixel stream. To prevent random color data from being displayed on the screen while the device performs these 4 writes, the data at POUT0-POUT23 will be held at the value defined by the last valid pixel address. When Pixel clock is much slower than 70 MHz, the operating frequency of MPU should also be slowed down accordingly in order to maintain the synchronization of FIFO operations Color Buffer Register The Color Buffer Register stores the red and green data that is written to the Color Palette Buffer. Thus if a complete red, green, blue write cycle is not completed (register data is not transferred to the Write FIFO), then the host can recover the red and green data it has written by reading the red and green Color Buffer Registers. The host can recover the red and green data by first writing to the address register to reset the RGB counter. Then the red and green data can be recovered in two consecutive reads of the Color Buffer Register.
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MOSEL VITELIC
Truth Table
R/WB 0 0 0 0 0 CONFIGSEL<2:0> 000 0 001 1 010 2 010 2 010 2 RGB14 x x 0 0 1 RGB04 x x 0 1 0 FUNCTION
MS622424
Write Address Register Low, reset RGB Counter Write Address Register High, reset RGB Counter (1) Write Red Color Palette Buffer, increment RGB counter Write Green Color Palette Buffer, increment RGB counter Write Blue Color Data to Write FIFO, transfer register contents to Write FIFO, reset RGB counter, increment Address Register Write Command Register Invalid Operation Invalid Operation Invalid Operation Initialize color palette read Read Address Register Low Read Address Register High (2) Read Red Color Palette, increment RGB counter (3) Read Green Color Palette Buffer, increment RGB counter Read Blue Color Palette Buffer, reset RGB counter, increment Address register Read Command Register Read Status Register Read Red Color Buffer Register, increment RGB counter Read Green Color Buffer Register Invalid Operation Read Revision Register Terminate color palette read
0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1
011 3 100 4 101 5 110 6 111 7 000 0 001 1 010 2 010 2 010 2 011 3 100 4 101 5 101 5 101 5 110 6 111 7
x x x x x x x 0 0 1 x x 0 0 1 x x
x x x x x x x 0 1 0 x x 0 1 0 x x
NOTE: 1. Only CONFIGBUS0-CONFIGBUS4 are recognized; the upper three bits are ignored. 2. Data is output to CONFIGBUS0-CONFIGBUS4 only. The upper three bits will output "0". 3. Reading the Red Color Palette may disturb the pixel stream. 4. RGB0 and RGB1 are internal RGB couter outputs.
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MOSEL VITELIC
Internal Registers
Command Register The Command Register is an 8-bit register.
CB5-CB7
MS622424
CB4 D7
CB3
CB2
CB1
CB0 D0
CB0 CB1 CB2 CB3 CB4
PIPE.IN0 reset PIPE.IN1 reset PIPE.IN2 set PIPE.IN3 set HFB/AFB
This bit is internally ANDed with PIPE.IN0 . Thus when CB0 is "0", then PIPE.OUT0 will always be "0" This bit is internally ANDed with PIPE.IN1 . Thus when CB1 is "0", then PIPE.OUT1 will always be "0" This bit is internally ORed with PIPE.IN2 . Thus when CB2 is "1", then PIPE.OUT2 will always be "1" This bit is internally ORed with PIPE.IN3 . Thus when CB3 is "1", then PIPE.OUT3 will always be "1" This bit programs the AFB flag indicator. When this bit is "0" the AFB pin will indicate that the FIFO is half full. When this bit is "1" AFB will indicate almost full. Reserved for internal use.
CB5-CB7
Reserved
Status Register
The Status Register is an 8-bit register.
SB5-SB7
SB4 D7
SB3
SB2
SB1
SB0 D0
SB0 SB1 SB2 SB3
RGB0 RGB1 EFB HFB/AFB
LSB of RGB counter. RGB0 and RGB1 form two bits of a modulo three counter that determines which color is operated on (read only). MSB of RGB data counter (read only). Empty Flag; Write FIFO is empty when this bit is low. Half or Almost-Full Flag; Like the external AFB pin, this bit can be programmed by CB4 to indicate that the Write FIFO is at least half full or at least 7/8 full (eight or fewer empty locations left). This pin is active low. Full Flag; Write FIFO is full when this bit is low. Reserved for internal use.
SB4 SB5-SB7
FFB Reserved
Revision Register
The Revision Register is an 8-bit register.
RVB4-RVB7
RVB3 D7
RVB2
RVB1
RVB0 D0
RVB0 RVB1 RVB2 RVB3 RVB4-RVB7
REV0 REV1 REV2 Reserved REV4-7
LSB of Revision Register. This register is mask programmed to indicate the revision number. Second bit of Revision Register. MSB of Revision Register. Reserved for internal use. Corresponds to board revision input BD.REV0-3
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MOSEL VITELIC
100-pin PQFP/MQUAD PIN CONFIGURATION Top View
PIX.RGB0 PIX.RGB1 PIPE.IN0 PIPE.IN1 PIPE.IN2 PIPE.IN3 VCC VCC BD.REV3 BD.REV2 BD.REV1 BD.REV0 VSS/TEST VSS VSS PIPE.OUT3 PIPE.OUT2 PIPE.OUT1 PIPE.OUT0 VCC
MS622424
PIXIN23 PIXIN22 PIXIN21 PIXIN20 PIXIN19 PIXIN18 VSS VSS CLOCK.IN PIXIN17 PIXIN16 PIXIN15 PIXIN14 PIXIN13 PIXIN12 VCC VCC PIXIN11 PIXIN10 PIXIN9 PIXIN8 PIXIN7 PIXIN6 PIXIN5 PIXIN4 PIXIN3 PIXIN2 PIXIN1 PIXIN0 VSS
1
81
MS622424
31
51
VCC POUT23 POUT22 POUT21 POUT20 VSS POUT19 POUT18 POUT17 POUT16 POUT15 POUT14 POUT13 POUT12 VSS POUT11 POUT10 POUT9 POUT8 VCC VCC POUT7 POUT6 POUT5 POUT4 VSS POUT3 POUT2 POUT1 POUT0
MS622424 Rev. 1.0 January 1995
CBLANKB CONFIGBUS0 CONFIGBUS1 CONFIGBUS2 CONFIGBUS3 VSS CONFIGBUS4 CONFIGBUS5 CONFIGBUS6 CONFIGBUS7 CEB1 CEB2 R/WB CONFIGSEL0 CONFIGSEL1 CONFIGSEL2 RSB FFB AFB VSS
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MOSEL VITELIC
Pin Descriptions
Pin Name PIXIN0-PIXIN23 Description
MS622424
These inputs are latched on the rising edge of CLOCK.IN. The PIXIN0-PIXIN23 can be utilized in two different modes. In the Color Index Mode, PIXIN0-PIXIN12 are used to look up a 24 bit color from a palette of 8192 colors; the higher order bits in this mode are ignored. In the RGB Mode, PIXIN0-PIXIN7, PIXIN8-PIXIN15, and PIXIN16-PIXIN23 will address a red, green, or blue color value, respectively, from the 8K color palette. Internally, the five higher order bits are appended to the 8-bit addresses to compose the necessary 13 bits to address 8K locations. The five appended bits can be one of three values:(1)11101, (2)11110, or (3)11111. These binary addresses are expressed with the most significant bit on the left. The RGB Mode and five higher order bits are determined by the values of PIX.RGB0 and PIX.RGB1.
PIX.RGB0-PIX.RGB1
These two input pins select Color Index Mode or RGB mode. The table below defines the selection associated with the values of these two bits. PIX.RGB1 PIX.RGB0 0 0 1 1 0 1 0 1 SELECTION Color Index Mode RGB Mode, 11101 + 8-bit address RGB Mode, 11110 + 8-bit address RGB Mode, 11111 + 8-bit address
These two bits are latched on the rising edge of CLOCK.IN. PIPE.IN0-PIPE.IN3 These four input pins are provided for the video timing signals such as CBLANKB and CSYNCB. Internally, these signals will go through the same number of pipeline stages as the pixel data. The video timing signals will subseqently appear at the PIPE.OUT outputs, and synchronized with the appropriate color data. These inputs are also latched by the rising edge of CLOCK.IN. This is the clock input pin. The CLOCK.IN controls the latching output and subsequent processing of the pixel data and video timing signals. Color information output pins. POUT0-POUT7, POUT8-POUT15, and POUT16- POUT23 are the red, green, and blue color data, respectively. Video timing signals output pins. The output data is synchronized with the color data is output on these pins. Fig. 1 describes internal pipeline data path flow. The chip enable input pins. MPU read and write cycles are performed by bringing either of these pins low. The falling edge of this signal latches information from the R/WB, CONFIGSEL, and CONFIGBUS pins. Read and write control input pins. When latched by the falling edge of CEB, this signal determines whether the following operation is a read or a write. A read operation is performed when this signal is high, and a write operation is performed when this signal is low. These pins are used for data I/O. RAM and register data are input and output through these pins. These pins are used for read and write to/from RAM and register. The device configuration input pins. These inputs specify the type of read or write operation to perform. The particular RAM or register operation is defined by the truth table. This information is latched on the falling edge of CEB. Blanking status input pin. This signal indicates to the device that a blanking period is taking place so it is therefore permissible to change data in the palette RAM. This pin is active low.
CLOCK.IN POUT0-POUT23 PIPE.OUT0-PIPE.OUT3 CEB1, CEB2
R/WB
CONFIGBUS0-CONFIGBUS7
CONFIGSEL0-CONFIGSEL2
CBLANKB
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MOSEL VITELIC
Pin Descriptions (Cont'd)
Pin Name RSB Description
MS622424
Reset input pin. This asynchronous system reset initializes state machines and resets the Address, Status, and Color Buffer registers. It also resets the Write FIFO so that it is empty of any contents. It resets command register bits CB2-CB7 and sets bits CB0-CB1. During a reset, CONFIGBUS0-CONFIGBUS7 are in tri-state. This pin is active low. The FIFO status output pin. This active low output indicates that the Write FIFO is half or almost full. This active low output can be programmed by a bit in the Command Register to indicate that the FIFO is at least half full or is almost full (eight or less empty locations left). The FIFO status output pin. This active low output indicates that the Write FIFO is full. This pin should be grounded for normal operation. Board revision input pins. These input pins can be pull-up to V DD or pull-down to VSS . The BD.REV data can be read though the revision register.
AFB
FFB VSS/TEST BD.REV(0-3)
CLOCK.IN
INPUT 24 4 LATCH 1
ADDRESS DECODER
SENSE AMPLIFIER
OUTPUT
PIX.IN(0-23) PIPE.IN(0-3)
POUT(0-23) LATCH 2 LATCH 3 LATCH 4 PIPE.OUT(0-3)
Internal Pipeline Data Path for Pixel and Pipe Input Data
MS622424 Rev. 1.0 January 1995
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MOSEL VITELIC
Absolute Maximum Ratings*
Symbol Parameter VDD VT PD tOPR tSTG Supply Voltage Terminal Voltage with Respect to VSS Power Dissipation 100% Duty Cycle Rating -0.5* to +7.0 -0.5* to VDD +0.5 TBD Units V V W C C
MS622424
Capacitance*
TA = 25C, f = 1 MHz Symbol CIN COUT Parameter Input Capacitance (VIN = 0V) Output Capacitance (VOUT = 0V) Typ. Max. Unit 5 8 pF pF
Operating Temperature -10 to +85 Storage Temperature -65 to +150
*Note: These parameters are sampled and not 100% tested.
*Note: Operation above absolute maximum rating can affect device reliability.
Recommended DC and Operating Characteristics
TA = 0C to 70C, V DD = 5.0V 5%, VSS = 0V, unless otherwise noted. See package thermal data on pg 10. Symbol VDD VSS VIH VIL I LI I LO I DD VOL VOH Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Dynamic Operating Current Output Low Voltage Output High Voltage 2.4 Min. 4.75 0.0 2.2 -0.5* -10 -10 Max. 5.25 0.0 VDD+.3 +0.8 10 10 300 0.4 Units V V V V A A mA V V VDD = 5.25V, VIN = VSS to VDD VOUT = VSS to VDD Outputs Open, f = fmax Active Outputs Open, IOL = 4.0 mA IOH = -1.0 mA Test Condition
* -3.5V for 20 ns pulse.
AC Test Loads
Signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.0V to 3.0V, output loading as shown in the diagram below.
VDD
AC Test Conditions
(Applies to READ and WRITE Cycle Timing) Input Pulse High Level Input Pulse Low Level Input Rise Time Input Fall Time
1000 Ohms
VIH = 3.0V VIL = 0.0V tR = 3 ns tF = 3 ns 1.5V CL = 40pF, 1 TTL 5V 5% 0 to +70C
Input and Output Reference Level Output Load
OUTPUT 40 pF 667 Ohms
VDD TA
Figure 2. Output Load
MS622424 Rev. 1.0 January 1995
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MOSEL VITELIC
Timing Waveforms of MPU Cycle
1 2 5 7 3 4 CEB1 CEB2 6 8
MS622424
R/WB CONFIGSEL0-2 CONFIGBUS0-7 CONFIGBUS0-7 (Read Cycle) AFB, FFB 9
AC Characteristics
At recommended operating conditions, unless otherwise noted.
Symbol 1 2 3 4 5 6 7 8 9 Parameter CEB Cycle Time CEB Pulse Width CONFIGSEL/BUS and R/WB Set-up before CEB low CONFIGSEL/BUS and R/WBHold after CEB low CONFIGBUS Data Access CONFIGBUS Data Hold CEB low to CONFIGBUS Lo-Z CEB high to CONFIGBUS Hi-Z Write cycle start to AFB, FFB low 5 10 10 65 Min. 80 65 0 10 65 Typ. Max. Unit ns ns ns ns ns ns ns ns ns 2, 3 2, 3 Notes
NOTES: 1. Applicable to all speed grades. 2. This parameter is sampled and not 100% tested. 3. Transition is measured 500mV from low or high voltage with load (see Figure 2).
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MOSEL VITELIC
Timing Waveforms of Pixel Port, CBLANKB, and RESET
1 2 CLOCK.IN PIXIN0-23 PIX.RGB0-1 PIPE.IN0-3 CBLANKB 3
MS622424
5 4
POUT0-23 PIPE.OUT0-3 6 7
RSB
AC Characteristics
At recommended operating conditions, unless otherwise noted.
-60 Symbol 1 2 3 4 5 Parameter CLOCK.IN Cycle Time CLOCK.IN Pulse Width high CLOCK.IN Pulse Width low Pixel Data Set-up before CLOCK.IN high Pixel Data Hold after CLOCK.IN high PIXIN0-23 PIX.RGB0-1 PIPE.IN0-3 CBLANKB 6 7 CLOCK.IN high to Data out RSB Pulse width Low 4.0 4.0 6.0 3.0 6.0 35.0 12.0 3.0 3.0 5.0 1.5 5.0 30.0 10.0 2.5 2.5 4.0 1.5 4.0 25.0 9.0 ns ns ns ns ns ns 1 Min. Typ. Max. Min. 16.7 6.0 6.0 2.0 14.3 5.0 5.0 1.0 -70 -80
Typ. Max. Min. Typ. Max. Unit Notes 12.5 4.0 4.0 1.0 ns ns ns ns
NOTES: 1. This signal can be completely asynchronous to the Pixel Port and the MPU Port.
MS622424 Rev. 1.0 January 1995
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MOSEL VITELIC
PACKAGE OUTLINES
100 pin PQFP
MS622424
0.124 Max
TOP VIEW
0.020/0.010
.742 REF 0.790/0.784 0.786/0.780
0.948/0.933
0.554/0.548 0.713/0.697
0.103 MAX
SIDE VIEW
0.006
END VIEW
0.486 REF
100 pin MQUAD
0.65[0.0256] TYP NON-ACCUM.
0.25[0.010] (4 PLCS)
3.000.18 [0.1180.007] 0.13[0.005] (4 PLCS) 0.380.13 [0.150.005]
PIN #1 I.D.
A
A
19.786 +0.15 -0.05 [0.779 +0.006 ] -0.002 23.900.20 [0.9410.008]
18.85 REF. [0.742 REF.]
VENT CAP C-BORE o3.17 [o0.125]
13.792 +0.15 -0.05 [0.543 +0.006 ] -0.002 17.900.20 [0.7050.008]
0.15 [0.006] 2.640.13 [0.1040.005]
SIDE VIEW
TOP VIEW
MS622424 Rev. 1.0 January 1995
8-11

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